Learn Electronics Standard TTL Information Pages

Ever try interactive learning?
The fun way to learn.
Download Part 1 it's FREE

Standard TTL logic levels

Operating conditions: V _CC 4.75 V min. to 5.25 V max.
74XX chips

PARAMETER	CONDITIONS	MIN	MAX	UNITS
Logic 1 input voltage	V_CC = min	2.0	--	V
Logic 0 input voltage	V_CC = min	--	0.8	V
Logic 1 output voltage	V_CC = min - - I_out = -0.4 mA	2.4	--	V
Logic 0 output voltage	V_CC = min - - I_out = 16 mA	--	0.4	V
Logic 1 input current	V_CC = min - - V_in = 2.4 V	--	0.04	mA
Logic 1 input current	V _CC = min - - V_in = 5.5 V	--	1	mA
Logic 0 input current	V_CC = min - - V _in = 0.4 V	--	- 1.6	mA

What does it all mean?

V_OH Min = Output voltage high minimum with up to 0.4 mA load A good chip is guaranteed to output a minimum of 2.4 V logic high up to 0.4 mA

V_OL Max = Output voltage low maximum with up to 16 mA load A good chip is guaranteed to output a maximum of 0.4 volts up to 16 mA

V_IH Min = Input voltage high minimum 2.0 V A good chip will recognize 2.0 V or greater as a logic high and draw no more than 0.04 mA input current.

V_IL Min = Input voltage low maximum 0.8 V A good chip will recognize 0.8 V or less as a logic low and draw no more than 1.6 mA input current.

Fan out

For a logic high, a good chip will source 0.4 mA and maintain a minimum of 2.4 V
For a logic high, the input will draw no more than 0.04 mA
This means that a high output of a good chip will drive 10 inputs high.

For a logic low, a good chip will sink 16 mA and hold the voltage at 0.4 V maximum.
For a logic low, the input will draw no more than 1.6 mA
This means that a low output of a good chip will drive 10 inputs low.

This is what is meant by a Fan Out of 10.
Any Standard TTL chip that does not meet these specifications is defective and should be replaced.

Noise Margin

Notice the 400 mV difference between the specified output voltage of a TTL chip and the input voltage required to recognize a logic level. This 400 mV difference provides a margin such that noise added to the signal does not cause errors. An output voltage with up to 400 mV peak of noise added will still provide a valid logic level to the input of the next stage.